The present invention relates to method and apparatus for translating an address of a computer system which adopts a virtual memory scheme, and more particularly to method and apparatus for controlling multiple virtual spaces suitable for address translation where there is a common area among a portion of the virtual address space in a multiple virtual storage system.
In the computer system of the virtual memory scheme, a memory address is given by an address on a virtual space (that is, a logical address). Accordingly, when a main storage is to be accessed, it is necessary to translate the logical address to an address on the main storage (that is, a real address). The address translation is carried out by looking up an address translation table (usually comprising a segment table and page tables) provided in the main storage. Pairs of logical addresses and real addresses obtained by the address translation are usually registered or stored in an address translation buffer or translation lookaside buffer (TLB), and for the logical address requested for the memory access, the corresponding real address is looked up from the TLB so that the address translation is carried out at a high speed.
On the other hand, in a multi-process multiple virtual storage system, a virtual space is allotted for each job and an address translation table is provided for each virtual space. Switching of virtual spaces due to switching of jobs is carried out under control of an operating system (OS) of a computer system, such as Hitachi VOS3, by rewriting a start address of the address translation table or rewriting a content of an address control register (ATOR) which holds a space identifier. In this case, in addition to the logical address (LA) and the real address (RA), the content (ATO) of the address control register are held in the TLB. When the object real address is to be looked up from the TLB, the coincidence of the corresponding virtual spaces as well as the coincidence of the logical addresses is checked.
In such a multiple virtual storage system, a common area to respective virtual spaces is indicated by adding a common segment bit (C bit) in the TLB. When the C bit is "1" (indicating the presence of the common area), the start address of the address translation table or the space identifier held in the TLB is ignored, and if the logical address from the memory address register and the logical address of the TLB are equal, the corresponding real address is considered valid and the accessing to the main storage is carried out thereby. In the multiple virtual computer system, a computer identifier (CN bit) is set to an area common to the virtual computers, and a pair consisting of a logical address and a real address registered in the TLB is rendered valid by a logical product (AND) condition of the C bit and the CN bit.
This type of virtual space control system is shown in JP-A-60-68443 filed by the assignee of the present application and published on Apr. 19, 1985.
The prior art described above is effective in enhancing a hit rate of the address translation buffer when the common area which is common to all virtual spaces is used, but it does not give consideration to a case where there is a common area among a portion of virtual spaces. When the common area is set for the portion of virtual spaces, the hit rate of the address translation buffer decreases and the number of times of rewriting of the buffer increases. Data in the common area can be readily read from or updated by any virtual space so that security for the data and programs of the respective virtual spaces is not sufficiently assured. Accordingly, the prior art system is hardly applicable to an area which is to be shared by only specified spaces.